1.Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in a CMOS circuit.
2. Discussion of the Related Art
In general, as a semiconductor device becomes more highly integrated, the channel length of an MOS transistor becomes shorter. Accordingly, the channel break-down voltage decreases and a high-output voltage is not generated. Therefore, a conventional semiconductor is provided to solve the problem as follows.
As illustrated in FIG. 1, a conventional semiconductor device for generating high-output voltage includes a first PMOS transistor P1 having a gate for receiving a threshold voltage VSHLD for controlling its operation, and a source for receiving an input signal. A second PMOS transistor P2 has a gate for receiving a signal output from the drain of the first PMOS transistor P1 and a source for receiving a predetermined positive voltage VDD. A third PMOS transistor P3 has a source for receiving a signal output from the drain of the second PMOS transistor P2 and a gate for receiving the threshold voltage VSHLD. A first NMOS transistor N1 has a gate for receiving the threshold voltage VSHLD and a drain for receiving the input signal. A second NMOS transistor N2 has a gate for receiving a signal output from the source of the first NMOS transistor N1 and a source for receiving a ground potential. A third NMOS transistor N3 has a source connected to the drain of the second NMOS transistor N2, a drain for receiving the voltage of the drain of the third PMOS transistor P3, and a gate for receiving the threshold voltage VSHLD.
Here, the substrate bias voltage of the first through third PMOS transistors P1 to P3 is fixed as the positive voltage VDD. The substrate bias voltage of the first to third NMOS transistors N1 to N3 is fixed as the ground potential.
The thus-structured conventional semiconductor device for preventing a channel break-down is shown in U.S. Pat. No. 5,465,054. Now, the operation of the above-mentioned device will be described below.
If the threshold voltage is set to 5 V DC and the positive voltage VDD for operating the transistor is set to 10 V, the first and third PMOS transistors P1 and P3 and the first and third NMOS transistors N1 and N3 are constantly turned on. Here, the second NMOS transistor N2 and PMOS transistor P2 are separately turned on/off according to the input voltage state. Accordingly, if the input voltage is at a low level, the second PMOS transistor P2 is turned on while the second NMOS transistor N2 is turned off. Therefore, the positive voltage VDD (the operation voltage) is applied to the common drain of the third PMOS and NMOS transistors P3 and N3, thereby maintaining the high level.
On the other hand, if the input voltage is at a high level, the second PMOS transistor P2 is turned off while the second NMOS transistor N2 is turned on. Therefore, the ground voltage is applied to the common drain of the third PMOS and NMOS transistors P3 and N3, thereby maintaining the low level. Here, although the potential state of the input signal is classified into the low and high levels, the voltage states are relative and do not specifically mean 0 V or 5 V.
As described above, even though the output voltage varies from 0 V to 10 V, the voltages between the source and the drain of each of the second and third PMOS transistors P2 and P3 for performing a pull-up function, and of the second and third NMOS transistors N2 and N3 for performing a pull-down function are both restricted to 5 V. This is so that the circuit can prevent the transistor channel break down due to the variation of the output voltage. Therefore, the circuit may generate an output voltage that is two times the channel break-down voltage.
However, in such a conventional semiconductor device, if the positive operation voltage VDD is increased to 10 V through 15 V to obtain the very high-output voltage, the voltages between the source and the drain of each of second and third PMOS transistors P2 and P3 and of the second and third NMOS transistors N2 and N3 become about 7.5 V. Moreover, if the operation positive voltage VDD is increased to 30 V, the voltage between the source and drain becomes about 15 V. When the operation positive voltage VDD is excessively increased, the sources and drains of the transistors P2, P3, N2, N3 also receive the excessively increased voltage. Accordingly, those transistors experience a channel break-down, resulting in circuit malfunction. As a result, when the increasing range of the operational positive voltage is more than a predetermined threshold voltage, the conventional circuit cannot output a voltage of more than two times the channel break down voltage.